The present invention relates generally to a semiconductor integrated circuit including a power on clear (POC) circuit and more particularly to a semiconductor integrated circuit including a circuit that may prevent data destruction in a random access memory (RAM) caused by a reset operation or the like.
Semiconductor integrated circuits can include a power on clear (POC) circuit. A POC circuit is intended to detect a power up and set circuitry to a known state as necessary to ensure proper operation. Cases in which a POC circuit has been included on a semiconductor integrated circuit include a semiconductor integrated circuit in a remote control, a battery driven microcomputer, or the like.
A remote control including a POC circuit includes a ROM (read only memory) that stores data that can be used to configure the remote control waveform for a number of respective manufacturers and/or devices. This data is provided in a remote control so that a single remote control can have the capability of operating various devices and/or similar devices made by differing manufacturers. A remote control also includes a RAM (random access memory). The RAM is used to store data set by a user.
Referring now to FIG. 4, a circuit schematic diagram of a conventional semiconductor integrated circuit is set forth and given the general reference character 400. Conventional integrated circuit 400 is a portion of a remote control including a RAM.
RAM memory cells 101 include transistors (102 and 103) and flip-flops 104. Transistors (102 and 103) form transfer gates for each RAM memory cell 101. Transistors (102 and 103) have control gates commonly connected to a word line 108. Transistor 102 has a source/drain connected to bit line (/Q) 105 and another source/drain connected to a first node of flip-flop 104. Transistor 103 has a source/drain connected to bit line (Q) 106 and another source/drain connected to a second node of flip-flop 104. Flip-flop 104 includes a first and second inverter, with the first inverter having an output connected to the input of the second inverter at the first node and the second inverter having an output connected to an input of the first inverter at the second node.
RAM memory cells 101 are static random access memory (SRAM) cells.
A combination circuit 107 receives an address signal and other control signals and activates a respective word line 108. In this way, a respective memory cell 101 is selected.
In the conventional remote control including a RAM, as illustrated in conventional semiconductor integrated circuit 400, a POC circuit can be installed in the semiconductor integrated circuit 400 or attached externally to the semiconductor integrated circuit 400.
In a conventional remote control, when a reset is initiated by a POC circuit, the conventional remote control initializes the RAM data.
However, if a reset is initialized by a POC circuit, the data in the RAM can still be held unless a power supply voltage drops lower than a RAM holding voltage. A RAM holding voltage is a minimum voltage at which the RAM can reliably hold data in the memory cells. In this case, the integrity of the RAM data could still be reliable.
However, even if the RAM data is being held, the integrity of the data can be compromised when the POC circuit is asynchronously affected (for example, by a power supply fluctuation, or the like).
In other words, when reset by a POC circuit, for example, at the time RAM data is being accessed, word lines other than word lines for the access data may also become enabled (activated to select a memory cell) due to transitions of the address signal due to the reset. In this way, transistors (102 and 103) for memory cells not intentionally accessed can be turned on. This can lead to destruction of the RAM data, by for example, overwriting data in a memory cell with data on the bit lines (105 and 106). When a reset operation as described above, destroys data in the RAM, undesirable effects can occur.
In view of the above discussion, it would be desirable to provide a semiconductor integrated circuit that may prevent the destruction of RAM data due to a reset that may occur when operating conditions may allow data to be reliably held.
According to the present embodiments, a semiconductor integrated circuit that may determine whether or not a power supply voltage has dropped to a level that data integrity in a RAM portion may be lost. The semiconductor integrated circuit may include a POC circuit, a low voltage detecting circuit, a RAM data destruction preventing block, a RAM portion, and a combination circuit. A power on clear (POC) circuit may detect when a power supply potential is below a predetermined voltage and provide a reset signal to a RAM data destruction preventing block. A RAM data destruction preventing block may prevent access to memory cells in the RAM portion in response to the reset signal. A low voltage detecting circuit may determine if the power supply potential may have dropped below a data holding voltage. In this way, data may only be rewritten to a RAM portion after a reset operation if data integrity may be lost
According to one aspect of the embodiments, a semiconductor integrated circuit may include a random access memory (RAM), a power on clear circuit, a first circuit, a second circuit, and a third circuit. RAM may include a plurality of word lines. A power on clear circuit may provide a reset signal. A first circuit may receive the reset signal and render the plurality of word lines in a non-select state when the reset signal is in a reset state. A second circuit may receive the reset signal and provide a system reset signal after a predetermined delay. A third circuit may determine whether or not a power supply potential has dropped below a low voltage detection potential. When the reset signal is in the reset state, a system may be reset after the plurality of word lines are in the non-select state.
According to another aspect of the embodiments, the third circuit may include a comparator. The comparator may compare the power supply potential with the low voltage detection potential and provide a low voltage detection flag.
According to another aspect of the embodiments, the third circuit may include a first RAM memory cell having a first transfer gate. The RAM may include a second RAM memory cell having a second transfer gate. A threshold voltage of the first transfer gate may be higher than a threshold voltage of the second transfer gate.
According to another aspect of the embodiments, the first circuit may receive an external reset signal and an address value. The first circuit may render the plurality of word lines in the non-select state when the external reset signal is in an external reset state. The first circuit may render at least one word line to a select state in response to the address value when the external reset signal is in an external non-reset state and the reset signal is in a non-reset state.
According to another aspect of the embodiments, the first circuit may include a first logic circuit and a second logic circuit. The first logic circuit may receive the external reset signal and the reset signal and provide an internal reset signal. The second logic circuit may receive the internal reset signal and the address value and provide the state of at least one word line.
According to another aspect of the embodiments, the first circuit may receive an external reset signal and a control signal. The first circuit may render the plurality of word lines in the non-select state when the external reset signal is in an external reset state.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a random access memory (RAM), a first voltage level detection circuit, a first circuit, and a second voltage detection circuit. A RAM may include a plurality of memory cell selection signals. A first voltage level detection circuit may provide a first voltage level detection signal having a first voltage level logic level when a power supply potential is greater than a first detection potential and a second voltage level logic level when the power supply potential is less than the first detection potential. A first circuit may receive the first voltage level detection signal and provide the plurality of memory cell selection signals in a memory cell unselected state when the first voltage level detection signal has the second voltage level logic level. A second voltage detection circuit may detect when a power supply potential is less than a second detection potential and provide a low voltage level indicator. The second detection potential may be lower than the first detection potential.
According to another aspect of the embodiments, a semiconductor integrated circuit may provide the low voltage level indicator to a processor. The processor may rewrite data to the RAM after the low voltage level indicator is provided.
According to another aspect of the embodiments, the semiconductor integrated circuit may provide the first voltage level detection signal to a processor and the RAM may have the data rewritten when the first voltage level detection signal has the first voltage logic level after the low voltage level indicator is provided.
According to another aspect of the embodiments, the low voltage level indicator may be latched in a register and sampled in response to the first voltage level detection signal having the first voltage logic level.
According to another aspect of the embodiments, a delay circuit may receive the first voltage level detection signal and provide a system reset signal after a predetermined delay.
According to another aspect of the embodiments, the first circuit may receive an address value and activate one of the selection signal in accordance with the address value when the first voltage level detection signal has the first voltage level logic level.
According to another aspect of the embodiments, the second voltage level indicating circuit may include a comparator. The comparator may receive the power supply voltage at one compare input terminal and a reference potential at another compare input terminal and provide the low voltage level indicator.
According to another aspect of the embodiments, a semiconductor integrated circuit may include a random access memory (RAM), a first voltage level detection circuit, a first circuit, and a second voltage detection circuit. A RAM may receive at least one control signal. A first voltage level detection circuit may provide a first voltage level detection signal having a first voltage level logic level when a power supply potential is greater than a first detection potential and a second voltage level logic level when the power supply potential is less than the first detection potential. A first circuit may receive the first voltage level detection signal and provide the at least one control signal in a RAM unselected state when the first voltage level detection signal has the second voltage level logic level. A second voltage detection circuit may detect when a power supply potential is less than a second detection potential and provide a low voltage level indicator. The second detection potential may be lower than the first detection potential.
According to another aspect of the embodiments, the second voltage level indicating circuit may include a comparator. The comparator may receive the power supply voltage at one compare input terminal and a reference potential at another compare input terminal and provide the low voltage level indicator.
According to another aspect of the embodiments, the second voltage level indicating circuit may include a first RAM memory cell having a first transfer gate. The RAM may include a second RAM memory cell having a second transfer gate. A threshold voltage of the first transfer gate may be higher than a threshold voltage of the second transfer gate.
According to another aspect of the embodiments, the first circuit may receive an external reset signal and provide the at least one control signal in the RAM unselected state when the external reset signal has an external reset logic level.
According to another aspect of the embodiments, the low voltage level indicator may be stored in a low voltage indicator register.
According to another aspect of the embodiments, a processor may sample the low voltage indicator register in response to the first voltage level detection signal having the first voltage level logic level.
According to another aspect of the embodiments, a processor may rewrite data in the RAM when the first voltage indicator register stores the low voltage level indicator and the first voltage level detection signal has the first voltage level logic level.